École Nationale des Sciences de
l’Informatique
Chapitre 5
Programmation de
périphériques
périphériques
Module : Introduction aux systèmes embarqués
Niveau : II2 – Tronc commun
AU : 2011/2012
OUTLINE
(cid:1) GPIO
(cid:1) GPIO features
(cid:1) GPIO configuration modes
(cid:1) Alternate functions
(cid:1) Alternate functions
(cid:1) EXTI
(cid:1) EXTI features
2
2
GPIO Features (1/2)
(cid:1) Up to 80 multifunction bi-directional I/O ports available
(cid:1) Standard I/Os 5V tolerant
(cid:1) The GPIOs can sink 25mA
(cid:1) 18 MHz Toggling
(cid:1) Configurable Output Speed up to 50 MHz
(cid:1) Up to 16 Analog Inputs
Up to 16 Analog Inputs
(cid:1) Alternate Functions pins (like USARTx, TIMx, I2Cx, SPIx,
CAN, USB…)
(cid:1) Up to 80 GPIOs can be set-up as external interrupt (up to 16 lines
at time)
(cid:1) One I/O can be used as Wake-Up from STANDBY (PA.00)
(cid:1) One I/O can be set-up as Tamper Pin (PC.13)
(cid:1) All Standard I/Os are shared in 5 ports (GPIOA..GPIOE)
3
GPIO Features (2/2)
(cid:1) Each of the general-purpose I/O ports has :
(cid:1) two 32-bit configuration registers (GPIOx_CRL, GPIOx_CRH),
(cid:1) two 32-bit data registers (GPIOx_IDR, GPIOx_ODR),
(cid:1) a 32-bit set/reset register (GPIOx_BSRR),
(cid:1) a 16-bit reset register (GPIOx_BRR)
(cid:1) and a 32-bit locking register (GPIOx_LCKR).
(cid:1) GPIOx_BSRR and GPIOx_BRR registers allow atomic read/modify
accesses to any of the GPIO registers
(cid:1) (cid:1) No risk that an IRQ occurs between the read and the modify access
(cid:1) Locking mechanism to avoid spurious write in the IO registers: When
the LOCK sequence has been applied on a port bit, it is no longer
possible to modify the configuration of the port bit until the next reset
(no write access to the CRL and CRH registers corresponding bit)
4
GPIO Configuration Modes
CNF1 CNF0 MOD1 MOD0
Publicité
Analog Input
To On-chip Peripherals
Alternate Function Input
Configuration
Mode
Analog Input
Input Floating
(Reset State)
Input Pull-Up(2)
Input Pull-
Input Pull-
Down(2)
Output
Push-Pull
Output
Open-Drain
AF Push-Pull
AF
Open-Drain
0
0
1
0
0
1
1
0
1
0
0
1
0
1
00
Read
01: 10 MHz
10: 2 MHz
11: 50 MHz
Write
t
e
s
e
R
/
t
e
S
t
i
B
s
Publicité
r
e
t
s
g
e
R
i
Read / Write
From On-chip Peripherals
r
r
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e
t
t
s
s
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g
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e
R
R
a
a
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p
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Publicité
a
t
a
D
t
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p
t
u
O
VDD
ON/OFF
ON
OFF
0
TTL Schmitt
Trigger
Input Driver
Output Driver
ON/OFF
VSS
VDD
P
U
-
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P
n
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w
w
o
o
D
D
-
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P
VDD or VDD_FT(1)
i
n
p
O
/
I
OUTPUT
CONTROL
VSS
Publicité
VSS
Push-Pull or
Open Drain
or disabled
(2) Input Pull-Up and Input Pull-Down are
differentiated by the PxODR.y bit
field.
Alternate Function Output
5
AFIO Features
(cid:1) GPIO Software Remapping
(cid:1) Some Alternate function can be remapped in two different pins
(cid:1) optimization of the pin number of peripherals available for the 64-pin or
the 100-pin or the 144-pin package
(cid:1) Pins of the following I/O can be used as GPIO (remapping)
• OSC32_IN/OSC32_OUT pins
• OSC_IN/OSC_OUT pins
• OSC_IN/OSC_OUT pins
• CAN1 /CAN2
• JTAG/SWD
• ADC
• Timer
• USART
• I2C1
• SPI1
• SPI3/I2S3
• Ethernet
6
EXTI features
(cid:1) Up to 19 Interrupt/Events requests
(cid:1) Up to 80 GPIOs can be used as
EXTI line(0..15)
(cid:1) EXTI line 16 connected to PVD output
(cid:1) EXTI line 17 connected to RTC Alarm
event
(cid:1) EXTI line 18 connected to USB Wake-up
from suspend event
from suspend event
(cid:1) Two Configuration modes:
(cid:1) Interrupt mode: generate interrupts with
external lines edges
(cid:1) Event mode: generate pulse to wake-up system
from SLEEP and STOP modes
(cid:1)
Independent trigger (rising, falling, rising & falling) and mask on each interrupt/event line
(cid:1) Dedicated status bit for each interrupt line
(cid:1) Generation of up to 19 software interrupt/event requests
7
EXTI features
8