HW/SW Co-design of embedded
systems
Chapter 1 : Introduction
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What is assumed ?
● Basic logic design
● Basic knowledge of Hardware Description
Languages
– VHDL
● Computer architecture basics
● Operating Systems
● Programming languages
– C, C++, ...
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Courses Goals
● Introduce the fundamentals of HW/SW codesign and
partitionning concepts in designing embedded systems (ES)
– Discuss the current trends in the codesign of ES
● Show benefits of the codesign approach over current design
process
● Illustrates how codesign concepts are being introduced into
design methodologies
– Design flows for systems-on-chip (SoC)
● Focus on higher level steps in the design flow
– The low level part is considered as more mature and less challenging
from a research point of view
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Outline
● Context : Embedded systems
● Target : System On Chip (SoC)
● Design challenges
● Solution : Co-Design flow
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Outline
● Context : Embedded systems
● Target : System On Chip (SoC)
● Design challenges
● Solution : Co-Design flow
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Definition
Embedded systems (ES) are information processing
systems embedded into a larger product [Peter
Marwedel]
Human interface
Embedded
System
Sensors / Actuators
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Examples
●Cell phone.
●Printer.
●Automobile: engine, brakes, audio, etc.
●Airplane: engine, flight controls, nav/comm.
●Digital television (HDTV, SmartTV).
●Household appliances.
●Medical systems
●Robot
●Military systems
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Automobile : 100 processors
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MPSOC Architecture example
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MPSOC Architecture example
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Ubiquitous computing
●Ubiquitous computing:
Information anytime, any-
where.
●Two enabling technologies
–Embedded systems
–Communication technology
●Examples :
–Sensor networks, smart products ...
ES
ES
Communication
infrastructure
ES
Publicité
ES
ES
ES
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Communicating Embedded Systems
● sensor networks (civil engineering, buildings, environmental
monitoring, traffic, emergency situations)
● smart products, wearable/ubiquitous computing
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PCs are not ES
● PCs (but also servers and super-computers) are
general purpose (GP) computing systems
● Main difference (common to all ES) :
– ES: fixed application (or set of applications) that is
known at design time
– GP : broad range of applications that are unknown at
design time (programmed by end-user)
● Additional differences (not common to all ES)
– Real-time, low power, low cost, safe, error-tolerant ...
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Real-time
●Real-time doesn't means fast but mean meeting time
constraints
●A real-time system must react to stimuli from the controlled
object (or the operator) within the time interval dictated by the
environment.
execute
t
●A real-time constraint is called hard, if not meeting that
constraint could result in a catastrophe
●All other time-constraints are called soft.
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Low power
● For battery operated embedded systems, battery life
is a killing factor
● Problem :
– More processing power generally means more energy
● Danger : Energy ~ Frequency² (don't rely on increasing
frequency)
– Advances in battery technology are slow compared to the
quick increase in processing power needs
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Low cost
● Most ES are sensitive to the cost factor
● Unit Cost = NR / N + R
– NR : non recurring cost
– R : recurring cost
– N number of units sold
● Time is money : Time-to-market factor
– Design time enters in :
● NR cost and thus unit cost (man.year)
● Market share
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Comparison
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Outline
● Context : Embedded systems
● Target : System On Chip (SoC)
● Problem Formulation
● Solution : Co-Design flow
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Need for a Design Flow
Specification
Implementation
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Integration & Moore's low
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Design evolution
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Implementation Alternatives (1)
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Implementation alternatives (2)
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Publicité
Implementation alternatives (3)
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Target implementation
● Pure Hardware
● Pure Software
● Mixed Hardware/Software
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Example : FFT
● Pure Hardware
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Example : FFT
● Pure Software
Cross-Compilation
Link
Download
CPU
MEM
I/O
static void FFT_R4(complex *xin, int N, int m)
{
int i, L, j;
double ps1, ps2, ps3;
int le,B;
struct complex w[4];
for( L = 1; L <= m; L++){
le = pow(4 ,L);
B = le/4; /the distance of buttefly/
for(j = 0; j <= B-1 ; j++)
{ ps1 = ((TWICEPI)/le)2j;
w[1].real = cos(ps1);
w[1].imag = -sin(ps1);
ps2 = (TWICEPI/le)*j;
w[2].real = cos(ps2);
w[2].imag = -sin(ps2);
ps3 = (TWICEPI/le)3j;
w[3].real = cos(ps3);
w[3].imag = -sin(ps3);
for(i = j; i <= N-1; i = i + le) / controle those same butteflies/
{
xin[i + B] = multicomplex(xin[i + B], w[1]);
xin[i + 2B] = multicomplex(xin[i + 2B], w[2]);
xin[i + 3B] = multicomplex(xin[i + 3B], w[3]);
/ DFT-4 /
DFT_4(xin + i, xin + i + B, xin + i + 2B, xin + i + 3B);
}
}
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Example : FFT
static void FFT_R4(complex *xin, int N, int m)
{
int i, L, j;
double ps1, ps2, ps3;
int le,B;
struct complex w[4];
init_configuration()
start_hardware_accelerator()
}
● Logiciel/Matériel
Cross-Compilation
Link
Download
HW
Accelerator
CPU
MEM
I/O
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Criteria : FPCE
● F : Flexibility
– How easy to change/upgrade the system ?
● P : Performance (Speed, Computation power)
● C : Cost (Design cost, Time-to-market)
● E : Energy (Power Efficiency)
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Implementation Matrix
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The Future...
● Software is getting more and more important
– Flexibility, upgrading, cost (time-to-market)
– Borrow code from software engineering
●
(Linux, GUI, Drivers...)
– Larger communities: HW developers considered as
Publicité
Gurus
● However, need to solve two problems
– Performance
– Energy consumption
→ Same Wall as General Purpose Computing today
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Outline
● Context : Embedded systems
● Target : System On Chip (SoC)
● Design challenges
● Solution : Co-Design flow
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Need for a Design Flow
Specification
Implementation
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Design methods
● To reduce design complexity, design methods and techniques
must be used. 3 methods can be employed.
● Top down method
– Begins from abstract description
– Enrichs description by details (refinement)
● Bottom up method
– regroups small components to obtain bigger systems
(abstraction).
● Platform method
– Combines both of them
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Typical design flow
ISA
Front-end
Validation
RTL
back-end
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Pure SW implementation
ISA
Front-end
Validation
RTL
back-end
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Pure HW implementation
ISA
Front-end
Validation
RTL
back-end
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Mixed HW/SW implementation
ISA
Front-end
Validation
RTL
back-end
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RTL/ISA : The ultimate frontier to System Design
● RTL : Register Transfer Level
– Hardware abstraction level
– Combination logic + registers
● ISA : Instruction Set Architecture
– Software abstraction level
– Low level (assembly) view of the CPU
●
Instructions, registers, addressing modes, exceptions...
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Front-end Vs Back-end
● Back-end : Logic Design or Synthesis
– Two steps
● Translate RTL to gates (logic optimisation)
● Translate gates to technology (mapping, place&route, layout)
– Mature domain : Many EDA tools exists on the market, with good
quality results
● Mentor, Cadence, Synopsys, Xilinx, Altera ...
● Front-end : System-Level Design or Synthesis
Publicité
– Translate input specification to low level architecture model (RTL/ISA)
– Still an active research area
– Objective of this course
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– Application Specification
– HW/SW Architecture design and exploration
– Validation and performance estimation
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Outline
● Context : Embedded systems
● Technology : System On Chip (SoC)
● Problem Formulation
● Solution : Co-Design flow
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Design / Codesign
Traditionnal design
Codesign (concurrent flow)
●
Independent groups of work
● Cooperation beween groups of
work
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Codesign definition and key concepts
● Codesign
– The meeting of system-level objectives by exploiting the
trade-offs between hardware and software in a system
through their concurrent design
● Key concepts
– Concurrent : hardware and software developed ate the
same time on parallel path
– Integrated: interaction between hardware and software
development to produce design meeting performance
criteria and functional specs
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Old design flow
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New design flow
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Example : magnetic tour counter
• 4 - sensors « hall effect » (mesure ¼ de tours)
• Input decoding
• GPP using for one input counting
• Filter realisation for each input
• Compute speed = f(nbre of tour)
• Output generation
• System constraints : area – 40 units, time – 100 cycles
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Purely sw design
• one processor for each input
– (-) area – 48 units > 40 units
– (-) time – 132 cycles > 100 cycles
– (+) Developement : 2 months
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Purley hw design
• HW filter (FIR), HW counters, decoders.
– (+) Area 24 units, < 40 units
– (+) Time – 52 cycles < 100 cycles
– (-) Developement : 9 months
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SW/HW codesign
• Codesign HW Multiplexing & filtering
– (+) area – 37 units, < 40 units
– (+) time – 95 cycles < 100 cycles
– (+) Developement : 3,5 mois
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