Review: Direct-mapped caches

 If the cache contains 2k

bytes, then the k least

significant bits (LSBs) are

used as the index.

– data from address i

would be stored in

block i mod 2k.

 For example, data from

memory address 11 maps

to cache block 3 on the

right, since 11 mod 4 = 3

and since the lowest two

bits of 1011 are 11.

Memory

Address

Index

Courtesy of Zilles

1998 Morgan Kaufmann Publishers

Review: Tags & Valid bits

 To find data stored in the cache, we need to add tags to distinguish

between different memory locations that map to the same cache block.

 We include a single valid bit per block to distinguish full and empty

blocks.

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

Index

Tag

Valid

Data

1998 Morgan Kaufmann Publishers

Review: How big is the cache?

For a byte-addressable machine with 16-bit addresses with a

cache with the following characteristics:

 It is direct-mapped (as discussed last time)

 Each block holds one byte

 The cache index is the four least significant bits

Two questions:

 How many blocks does the cache hold?

 How many bits of storage are required to build the cache (e.g.,

for the data array, tags, valid)?

1998 Morgan Kaufmann Publishers

Review: How big is the cache?

For a byte-addressable machine with 16-bit addresses with a cache with

the following characteristics:

 It is direct-mapped (as discussed last time)

 Each block holds one byte

 The cache index is the four least significant bits

Two questions:

 How many blocks does the cache hold?

4-bit index -> 24 = 16 blocks

 How many bits of storage are required to build the cache (e.g., for the

data array, tags, etc.)?

tag size = 12 bits (16 bit address - 4 bit index)

(12 tag bits + 1 valid bit + 8 data bits) x 16 blocks = 21 bits x 16 = 336

bits

1998 Morgan Kaufmann Publishers

More cache organizations

 Today, we’ll explore some alternate cache organizations.

– How can we take advantage of spatial locality too?

– How can we reduce the number of potential conflicts?

1998 Morgan Kaufmann Publishers

Memory System Performance

 To examine the performance of a memory system,

we need to focus on a couple of important factors.

– How long does it take to send data from the

cache to the CPU?

– How long does it take to copy data from memory

into the cache?

– How often do we have to access main memory?

 There are names for all of these variables.

– The hit time is how long it takes data to be sent

from the cache to the processor. This is usually

fast, on the order of 1-3 clock cycles.

– The miss penalty is the time to copy data from

main memory to the cache. This often requires

dozens of clock cycles (at least).

– The miss rate is the percentage of misses.

CPU

A little static

RAM (cache)

Lots of

dynamic RAM

1998 Morgan Kaufmann Publishers

Average memory access time

 The average memory access time, or AMAT, can then be

computed.

AMAT = Hit time + (Miss rate x Miss penalty)

This is just averaging the amount of time for cache hits and the

amount of time for cache misses.

 How can we improve the average memory access time of a

system?

– Obviously, a lower AMAT is better.

– Miss penalties are usually much greater than hit times, so the

best way to lower AMAT is to reduce the miss penalty or the

miss rate.

 However, AMAT should only be used a general guideline.

Remember that execution time is still the best performance

metric.

1998 Morgan Kaufmann Publishers

Performance example

 Assume the cache hit ratio is 97% and the hit time is one cycle,

but the miss penalty is 20 cycles.

AMAT = Hit time + (Miss rate x Miss penalty)

 How can we reduce miss rate?

1998 Morgan Kaufmann Publishers

Performance example

 Assume the cache hit ratio is 97% and the hit time is one cycle,

but the miss penalty is 20 cycles.

AMAT = Hit time + (Miss rate x Miss penalty)

= 1 cycle + (3% x 20 cycles)

= 1.6 cycles

 If the cache was perfect and never missed, the AMAT would be

one cycle. But even with just a 3% miss rate, the AMAT here

increases 1.6 times!

 How can we reduce miss rate?

1998 Morgan Kaufmann Publishers

Spatial locality

 One-byte cache blocks don’t take advantage of spatial locality,

which predicts that an access to one address will be followed by

an access to a nearby address.

 What can we do?

1998 Morgan Kaufmann Publishers

Spatial locality

 What we can do is make the cache block size larger than one

byte.

Memory

Address

 Here we use two-

byte blocks, so

we can load the

cache with two

bytes at a time.

 If we read from

address 12, the

data in addresses

12 and 13 would

both be copied to

cache block 2.

Index

1998 Morgan Kaufmann Publishers

Block addresses

 Now how can we figure out where data should be placed in the cache?

 It’s time for block addresses! If the cache block size is 2n bytes, we can

conceptually split the main memory into 2n-byte chunks too.

 To determine the block address of a byte

address i, you can do the integer division

Byte

Address

Block

Address

i / 2n

 Our example has two-byte cache blocks, so

we can think of a 16-byte main memory as

an “8-block” main memory instead.

 For instance, memory addresses 12 and 13

both correspond to block address 6, since

12 / 2 = 6 and 13 / 2 = 6.

1998 Morgan Kaufmann Publishers

Cache mapping

 Once you know the block address, you can map it to the cache as

before: find the remainder when the block address is divided by the

number of cache blocks.

 In our example,

memory block 6

belongs in cache

block 2, since

6 mod 4 = 2.

 This corresponds

to placing data

from memory

byte addresses

12 and 13 into

cache block 2.

Byte

Address

Block

Address

Index

1998 Morgan Kaufmann Publishers

Data placement within a block

 When we access one byte of data in memory, we’ll copy its entire block

into the cache, to hopefully take advantage of spatial locality.

 In our example, if a program reads from byte address 12 we’ll load all of

memory block 6 (both addresses 12 and 13) into cache block 2.

 Note byte address 13 corresponds to the same memory block address!

So a read from address 13 will also cause memory block 6 (addresses

12 and 13) to be loaded into cache block 2.

 To make things simpler, byte i of a memory block is always stored in

byte i of the corresponding cache block.

Byte

Address

Byte 0

Byte 1

Cache

Block

1998 Morgan Kaufmann Publishers

Locating data in the cache

 Let’s say we have a cache with 2k blocks, each containing 2n bytes.

 We can determine where a byte of data belongs in this cache by looking

at its address in main memory.

– k bits of the address will select one of the 2k cache blocks.

– The lowest n bits are now a block offset that decides which of the 2n

bytes in the cache block will store the data.

k bits

(m-k-n) bits

m-bit Address

Tag

Index

n-bit Block

Offset

 Our example used a 22-block cache with 21 bytes per block. Thus,

memory address 13 (1101) would be stored in byte 1 of cache block 2.

1 bit

2 bits

4-bit Address

1-bit Block

Offset

1998 Morgan Kaufmann Publishers

A picture

Address (4 bits)

Tag

Index (2 bits)

Block offset

Index

Valid

Tag

Data

Mux

Data

Hit

1998 Morgan Kaufmann Publishers

An exercise

Address (4 bits)

Index

Valid

Tag

Index (2 bits)

Data

0xCA

0xDE

0xBE

0xFE

0xAD

0xEF

0xED

Mux

Block offset

For the addresses

below, what byte is

read from the cache (or

is there a miss)?

1010

1110

0001

1101

Hit

Data

1998 Morgan Kaufmann Publishers

An exercise

Address (4 bits)

Index

Valid

Tag

Index (2 bits)

Data

0xCA

0xDE

0xBE

0xFE

0xAD

0xEF

0xED

Mux

Hit

Data

Block offset

For the addresses

below, what byte is

read from the cache (or

is there a miss)?

1010 (0xDE)

1110 (miss, invalid)

0001 (0xFE)

1101 (miss, bad tag)

1998 Morgan Kaufmann Publishers

Using arithmetic

 An equivalent way to find the right location within the cache is to use

arithmetic again.

m-bit Address

Tag

(m-k-n) bits

k bits

Index

n-bit Block

Offset

 We can find the index in two steps, as outlined earlier.

– Do integer division of the address by 2n to find the block address.

– Then mod the block address with 2k to find the index.

 The block offset is just the memory address mod 2n.

 For example, we can find address 13 in a 4-block, 2-byte per block

cache.

– The block address is 13 / 2 = 6, so the index is then 6 mod 4 = 2.

– The block offset would be 13 mod 2 = 1.

1998 Morgan Kaufmann Publishers

A diagram of a larger example cache

 Here is a cache with 1,024

blocks of 4 bytes each, and

32-bit memory addresses.

Address (32 bits)

2 bits

Index

Valid

Tag

Data

...

1022

1023

Tag

Mux

Data

Hit

1998 Morgan Kaufmann Publishers

A larger example cache mapping

 Where would the byte from memory address 6146 be stored in

this direct-mapped 210-block cache with 22-byte blocks?

 We can determine this with the binary force.

– 6146 in binary is 00...01 1000 0000 00 10.

– The lowest 2 bits, 10, mean this is the second byte in its

block.

– The next 10 bits, 1000000000, are the block number itself

(512).

 Equivalently, you could use your arithmetic instead.

– The block offset is 6146 mod 4, which equals 2.

– The block address is 6146/4 = 1536, so the index is 1536 mod

1024, or 512.

1998 Morgan Kaufmann Publishers

A larger diagram of a larger example cache mapping

Address (32 bits)

2 bits

0000 .... 0001

1000000000

Index

Valid

Tag

Data

...

512

...

1022

1023

Tag

Mux

Data

Hit

1998 Morgan Kaufmann Publishers

What goes in the rest of that cache block?

 The other three bytes of that cache block come from the same

memory block, whose addresses must all have the same index

(1000000000) and the same tag (00...01).

Address (32 bits)

0000 .... 0001

1000000000

Valid

Tag

Data

Index

...

512

...

Tag

Hit

Mux

Data

1998 Morgan Kaufmann Publishers

The rest of that cache block

 Again, byte i of a memory block is stored into byte i of the

corresponding cache block.

– In our example, memory block 1536 consists of byte addresses 6144

to 6147. So bytes 0-3 of the cache block would contain data from

address 6144, 6145, 6146 and 6147 respectively.

– You can also look at the lowest 2 bits of the memory address to find

the block offsets.

Block offset

Memory address

00..01 1000000000 00

00..01 1000000000 01

00..01 1000000000 10

00..01 1000000000 11

Decimal

6144

6145

6146

6147

Valid

Tag

Data

Index

...

512

...

1998 Morgan Kaufmann Publishers

Disadvantage of direct mapping

 The direct-mapped cache is easy: indices and offsets can be computed

with bit operators or simple arithmetic, because each memory address

belongs in exactly one block.

 But, what happens if a

program uses addresses

2, 6, 2, 6, 2, …?

Memory

Address

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

Index

1998 Morgan Kaufmann Publishers

Disadvantage of direct mapping

 The direct-mapped cache is easy: indices and offsets can be computed

with bit operators or simple arithmetic, because each memory address

belongs in exactly one block.

Memory

Address

 However, this isn’t really

flexible. If a program uses

addresses 2, 6, 2, 6, 2, ...,

then each access will result

in a cache miss and a load

into cache block 2.

 This cache has four blocks,

but direct mapping might

not let us use all of them.

 This can result in more

misses than we might like.

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

Index

1998 Morgan Kaufmann Publishers

A fully associative cache

 A fully associative cache permits data to be stored in any cache block,

instead of forcing each memory address into one particular block.

– When data is fetched from memory, it can be placed in any unused

block of the cache.

– This way we’ll never have a conflict between two or more memory

addresses which map to a single cache block.

 In the previous example, we might put memory address 2 in cache

block 2, and address 6 in block 3. Then subsequent repeated accesses

to 2 and 6 would all be hits instead of misses.

 If all the blocks are already in use, it’s usually best to replace the least

recently used one, assuming that if it hasn’t been used it in a while, it

won’t be needed again anytime soon.

1998 Morgan Kaufmann Publishers

The price of full associativity

 However, a fully associative cache is expensive to implement.

– Because there is no index field in the address anymore, the entire

block address must be used as the tag, increasing the total cache

size.

– Data could be anywhere in the cache, so we must check the tag of

every cache block. That’s a lot of comparators!

Address (32 bits)

Index

Valid

Tag (32 bits)

Data

...

Tag

Hit

1998 Morgan Kaufmann Publishers

Set associativity

 An intermediate possibility is a set-associative cache.

– The cache is divided into groups of blocks, called sets.

– Each memory address maps to exactly one set in the cache, but

data may be placed in any block within that set.

 If each set has x blocks, the cache is an x-way associative cache.

 Here are several possible organizations of an eight-block cache.

1-way associativity

8 sets, 1 block each

2-way associativity

4 sets, 2 blocks each

4-way associativity

2 sets, 4 blocks each

Set

1998 Morgan Kaufmann Publishers

2-way set associative cache implementation

 How does an implementation of a

2-way cache compare with that of

a fully-associative cache?

Address (m bits)

Tag

Index

(m-k-n)

Block

offset

Valid

Tag

Data

Valid

Tag

Data

Index

...

 Only two comparators are

needed.

 The cache tags are a little

shorter too.

Hit

2-to-1 mux

Data

1998 Morgan Kaufmann Publishers

Locating a set associative block

 We can determine where a memory address belongs in an associative

cache in a similar way as before.

 If a cache has 2s sets and each block has 2n bytes, the memory address

can be partitioned as follows.

Address (m bits)

(m-s-n)

Tag

Index

Block

offset

 Our arithmetic computations now compute a set index, to select a set

within the cache instead of an individual block.

Block Offset = Memory Address mod 2n

Block Address = Memory Address / 2n

= Block Address mod 2s

Set Index

1998 Morgan Kaufmann Publishers

Set associative caches are a general idea

 By now you may have noticed the 1-way set associative cache is the

same as a direct-mapped cache.

 Similarly, if a cache has 2k blocks, a 2k-way set associative cache would

be the same as a fully-associative cache.

1-way

8 sets,

1 block each

2-way

4 sets,

2 blocks each

4-way

2 sets,

4 blocks each

8-way

1 set,

8 blocks

Set

direct mapped

fully associative

1998 Morgan Kaufmann Publishers

Example placement in set-associative caches

 Where would data from memory byte address 6195 be placed, assuming

the eight-block cache designs below, with 16 bytes per block?

 6195 in binary is 00...0110000 011 0011.

 Each block has 16 bytes, so the lowest 4 bits are the block offset.

 For the 1-way cache, the next three bits (011) are the set index.

For the 2-way cache, the next two bits (11) are the set index.

For the 4-way cache, the next one bit (1) is the set index.

 The data may go in any block, shown in green, within the correct set.

1-way associativity

8 sets, 1 block each

2-way associativity

4 sets, 2 blocks each

4-way associativity

2 sets, 4 blocks each

Set

1998 Morgan Kaufmann Publishers

Block replacement

 Any empty block in the correct set may be used for storing data.

 If there are no empty blocks, the cache controller will attempt to replace

the least recently used block, just like before.

 For highly associative caches, it’s expensive to keep track of what’s

really the least recently used block, so some approximations are used.

We won’t get into the details.

1-way associativity

8 sets, 1 block each

2-way associativity

4 sets, 2 blocks each

4-way associativity

2 sets, 4 blocks each

Set

1998 Morgan Kaufmann Publishers

LRU example

 Assume a fully-associative cache with two blocks, which of the

following memory references miss in the cache.

– assume distinct addresses go to distinct blocks

Review: Caches in Memory Systems

Review: Caches in Memory Systems