Chapter on ARM Cortex-M4 and STM32F4xx MCU Architecture

USB 2.0 OTG

FS/HS

Ethernet MAC

10/100, IEEE1588

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5

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x

a

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A

AHB1

(max 168MHz)

Bridge

A

P

B

2

(

m

a

x

8

4

M

H

z

)

Bridge

APB1 (max 42MHz)

5x 16-bit Timer

2x 32-bit Timer

2x Watchdog

(independent & window)

1x SDIO

3x 12-bit ADC

24 channels / 2Msps

Temp Sensor

Encryption**

Camera Interface

USB 2.0 OTG FS

Power Supply

Reg 1.2V

POR/PDR/PVD

XTAL oscillators

32KHz + 8~25MHz

Int. RC oscillators

32KHz + 16MHz

PLL

RTC / AWU

4KB backup RAM

2x DAC + 2 Timers

2x CAN 2.0B

2 x SPI / I2S

4x USART/LIN

3x I2C

JTAG/SW Debug

ETM

Nested vect IT Ctrl

1 x Systic Timer

DMA

16 Channels

Clock Control

51/82/114/140 I/Os

2x6x 16-bit PWM

Synchronized AC Timer

3 x 16bit Timer

Up to 16 Ext. ITs

1 x SPI

2 x USART/LIN

OUTLINE

 Introduction

 ARM Cortex-M4 features

 Cortex-M3 Memory Map

 Cortex-M3 Interrupt Handling

 Cortex-M3 system peripheral

 Cortex-M3 based MCUs: The STM32F10x Family

14

14

14

Cortex M4 features

Interrupt controller:

-1 to 240 interrupts.

• 256 Priority levels
• NMI

-SysTick

CM4 Core:

Harvard (Separate Busses)

32 Bits Register & ALUs.

Thumb/thumb2

3 stage pipeline

Memory Protection Unit

(8 regions)

Multi layer Bus Matrix

(Parallel transfers

between core, memory, &

peripherals

Embedded Trace

MacroCell

Up to 240 Wake-up

Interrupts

Floating Point Unit:

Single precision FPU

IEEE 754 compliant

4 Watch points

Debug Access port

8 Hardware Breakpoints

Integrated Trace module:

Low cost (2 wires)

15

ARM Cortex-M4 Features

 ISA Support : Thumb® / Thumb-2

 Mix of 16 and 32 bit instructions for very high code density

 DSP Extensions

 Single cycle 16,32-bit MAC

 Single cycle dual 16-bit MAC

 8,16-bit SIMD arithmetic

 Hardware Divide (2-12 Cycles)

 Floating Point Unit: Single precision floating point unit, IEEE 754 compliant

 Pipeline : 3-stage + branch speculation

 Performance Efficiency : 2.19 CoreMark/MHz - 1.25 DMIPS/MHz

 Memory Protection : Optional 8 region MPU with sub regions and background region

 Interrupts

 Non-maskable Interrupt (NMI) + 1 to 240 physical interrupts

 Interrupt Priority Levels : 8 to 256 priority levels

 Wake-up Interrupt Controller : Up to 240 Wake-up Interrupts

 Sleep Modes

 Integrated WFI and WFE Instructions and Sleep On Exit capability.

 Sleep & Deep Sleep Signals.

 Optional Retention Mode with ARM Power Management Kit

 Debug: Optional JTAG & Serial-Wire Debug Ports. Up to 8 Breakpoints and 4 Watchpoints.

 Trace: Optional Instruction Trace (ETM), Data Trace (DWT), and Instrumentation Trace (ITM)

16

Thumb-2 Instruction Set

17

ARM performance + Thumb code density = Thumb-2

 No mode switching requirement like ARM7 core

17

Cortex-M4 Core Features

Thumb®-2 and traditional Thumb

18

18

Thumb extension

19

•Example of instruction conversion

• Thumb-instruction ADD Rd,#constant is converted to unconditionally

executed ARM-instruction ADD Rd,Rn,#constant

•Only the lower register set is in use so the upper register bit is fixed to

zero The constant is also 8-bit instead of 12-bit available in ARM-mode

OUTLINE

 Introduction

 ARM Cortex-M4

 Cortex-M4 Memory Map

 Cortex-M4 Interrupt Handling

 Cortex-M4 Specificities

 Cortex-M4 based MCUs: The STM32F4xx Family

20

20

20

Memory map : 4 GByte linear Memory space

Firmware : code nécessaire agissant

à très bas niveau (Driver) et

permettant aux applications

d’utiliser le matériel d’une façon

transparente

Espace utilisé pour adresser les

périphériques du Cortex-M4 :

Contrôleur d’interruption, le Timer

système, le bloc de contrôle, etc.

adresser des périphs externes :

carde SD,…

Espace utilisé pour adresser des

mémoires externes : external DDR,

Flash, LCD...

Espace utilisé pour adresser les

périphériques ajoutés par le

constructeur du microcontrôleur

intégrant le Cortex-M4: ADC, DMA,

Timer, etc

Espace utilisé pour stocker les

données relatives au code.

Espace utilisé pour stocker du code

exécutable. On peut également stocker

des données.

22/09/2019

Ben Fradj Hanene

21

Memory Map

22

Memory Map : Example

23

OUTLINE

 Introduction

 Cortex-M4 features

 Cortex-M4 Memory Map

 Cortex-M4 Interrupt Handling

 Cortex-M4 system peripherals

 Cortex-M4 based MCUs: The STM32F40x Family

24

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Cortex-M4: Interrupt Handling

▪ Le controlleur d'interruption: un

éléments essentiels d'un MCU

▪ permet de décharger le processeur

(minimiser son travail de traitement

logiciel), pour laisser des actions se

faire de manière matérielle.

▪ Typiquement, surveiller l'etat d'un

périphérique est inutile. Mieux vaut

laisser au périphérique le soin de

signaler lui-meme son etat.

 → le système d'interruptions (IC):

permet la mise en place de ce type de

dialogue coeur – périphérique, et

donner “l'autonomie” au

périphérique.

 Chaque periph est relié au IC par un

fil de sortie sur une borne donné

appelé interrupt request IRQ .

25

Cortex-M4: Interrupt Handling

▪ Le NVIC est capable de gérer :

jusqu’à 240 interruptions générées par

1.

des périphériques externes au Cotex-M4 +

NMI

▪ et dont

le niveau de priorité de

chacune peut être dynamiquement fixé

parmi 256 niveaux possibles.

latence

→faible

d’interruption

(implémentation hardware de push et

pop)

• exemple : fin de conversion par ADC,

erreur de receptionUSART, Timer …..

2. En plus de ces interruptions, le NVIC gère

d’exceptions:

certain

un

déclenchées

périphériques

internes du Cortex-M4 (Bus AHB, MPU,

Timer SysTick, etc..) ou par des fautes au

niveau du programme même.

nombre

des

par

processeur

→Le

sauvegarde

automatiquement son contexte et

le

restaure à la sortie de l’exception sans

aucune pénalité temporelle.

26

Cortex-M4: Interrupt Handling

Exceptions

•Asynchronous Exceptions = Interrupts

Generated by hardware peripherals (when enabled):

• Signal toggle (P I/O ports).
• Data receive (Serial peripherals)
• A/D conversion finished (DAC)
• Systick …….

•Synchronous Exceptions = Exceptions

Software origine . Generated after instruction execution errors such as:

• unauthorized Memory region access.
• Overflow.
• Divide by 0.
• …..

27

Interrupt Latency

28

Interrupt Latency

IRQ

PUSH

12

cycles

ISR

POP

12

cycles

Save Registers

(Hardware)

R0-R3 ; R12

R15 (Program Counter)

R14 (Link register)

PSR (Registre d’état)

Restore Registers

(Hardware)

For the ARM7 architecture ( Cortex-M predecessor), The PUSH

and POP operations were coded in assembler and they last 26 cycles

Cortex-M4: Interrupt Handling

relié au CSS du périphérique RCC asynchrone

synchrone

synchrone

synchrone

asynchrone

asynchrone

29

Cortex-M4: Interrupt Handling

Exceptions Vector Table

Exception

nbr

Address

Offset Exception

Vector

18–255

0x48–0x3FF IRQ #2–239

▪ Contient l’adresse de ISR à exécuter

si l’interruption survient

▪Quand une exception autorisée est

le CPU commence par

déclenchée,

récupérer

l’adresse de la routine à

exécuter à partir d’un emplacement

mémoire spécifique connu d’avance.

17

16

15

14

13

12

11

0x44

0x40

0x3C

0x38

0x34

0x30

0x2C

IRQ #1

IRQ #0

SYSTICK

PendSV

Reserved

Debug Monitor

SVC

7–10

0x1C–0x28

Reserved

▪ L’ensemble des adresses des routines

sources

relatives

d’interruptions

table de

la

vecteurs d’interruptions.

différentes

forme

aux

le Cortex-M4,

▪ Dans

la table de

vecteurs commence à partir de l’adresse

0 de la zone code :

6

5

4

3

2

1

0

0x18

0x14

0x10

0x0C

0x08

0x04

0x00

Usage fault

Bus fault

MemManage fault

Hard fault

NMI

Reset

Starting value

of the MSP

30

Exception Table vector

La table des vecteurs :

est une zone mémoire dont chaque

vecteur (32 bits pour un processeur 32

bits) précise le point d’entrée (adresse) de

la routine d’interruption ISR à exécuter en

cas d’occurrence d’une exception du

processeur.

ز

31

OUTLINE

 Introduction

 Cortex-M4 feastures

 Cortex-M4 Memory Map

 Cortex-M4 Interrupt Handling

 Cortex-M4 Specificities

 Power management

 System Timer

 Debug Capabilities

 Cortex-M4 based MCUs: The STM32F4xx Family

32

32

32

Power management

33

▪ Optimized RUN mode CORE power consumption

Cortex-M4: SysTick ‘System Timer’ (1/1)

 Flexible system timer

 24-bit self-reloading down counter with end of count interrupt

generation

 2 configurable Clock sources

 Suitable for Real Time OS or other scheduled tasks

In STM32F10x the SysTick clock can be: CPU clock or CPU clock/8

(provided externally by the Reset Clock Control )

CPU clock

1/8

SysTick clock

Down counter 24bits

Flag

Interrupt

34

Reset Clock Control

Cortex-M4: Debug Capabilities (1/1)

▪ Serial Wire Debugging for optimized device pin-out

M

T

E

G

A

T

J

SWD

More pins available

for the application

▪ Embedded break/watch capabilities for easy flashed application debugging

♦ 2 hardware breakpoints → 8 hardware breakpoints

♦ 2 hardware watchpoints

▪ Serial Wire Viewer for targeted low bandwidth data trace

♦ Using serial wire interface or dedicated bus CKout+D[3..0] for better bandwidth

♦ Triggered by embedded break and watch points

▪ ETM (Embedded Trace Macrocell) capability for better real time debugging

♦ Instruction trace only

♦ External signal triggering capability

♦ Can be used in parallel with data watchpoint

▪ Debugging features still kept whilst the core entered low power mode

35

Cortex-M4: Debug Capabilities

(1/1)

 JTAG

 JTAG is the industry-standard interface used to download and debug progams on a

target processor, as well as many other functions. It offers a convenient and easy way

to connect to devices and is available on all ARM processor-based devices.

 The JTAG interface can be used with Cortex-M4 devices to access all of the CoreSight

debug capabilities.

 Serial Wire Debug (SWD)

 The Serial Wire Debug mode is an alternative to the standard JTAG interface.

 SWD uses 2-pins to provide the same debug functionality as JTAG with no

performance penalty, and introduces data trace capabilities with the Serial Wire

Viewer (SWV).

 The SWD interface pins can be overlayed with the JTAG signals, allowing the

standard target connectors to be used.

 TCLK - SWCLK (Serial Wire Clock)

 TMS - SWDIO (Serial Wire debug Data Input/Output)

 TDO - SWO (output pin for Serial Wire Viewer. )

36

Cortex-M4: Debug Capabilities

37

Cortex-M4: Debug Capabilities

(1/1)

 Debug features:

 Run Control of the processor allowing you to start and stop programs

 Single Step one source or assembler line

 Set breakpoints while the processor is running

 Read/write memory contents and peripheral registers on-the-fly

 Program internal and external FLASH memory

 Trace features:

 Serial Wire Viewer (SWV) provides PC Sampling, data trace, event

trace, and instrumentation trace information

 Instruction (ETM) Trace streamed directly to your PC enabling

debugging of historical sequences, software profiling, and code

coverage analysis

M

T

E

G

A

T

J

SWD

More pins available

for the application

38

Cortex-M4: Debug Capabilities

 Serial Wire Viewer (SWV)

 Cortex-M4 based devices are able to provide high-speed data trace

information in a number of ways depending on the type of information

or analysis you require.

 The Serial Wire Viewer (SWV) provides real-time data trace

information from various sources within the Cortex-M4 device. This is

output via the single SWO pin while your system processor continues

running at full speed.

 Information is available from the ITM (Instrumentation Trace

Macrocell) and DWT (Data Watchpoint and Trace) units, providing:

 PC (Program Counter) sampling

 Event counters that show CPU cycle statistics

 Exception and Interrupt execution with timing statistics

 Trace data - data reads and writes used for timing analysis

 ITM trace information used for simple printf-style debugging

39

OUTLINE

 Introduction

 Cortex-M4 feautures

 Cortex-M4 Memory Map

 Cortex-M4 Interrupt Handling

 Cortex-M4 system peripherals

 Cortex-M4 based MCUs: The STM32F4xx Family

40

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STM32 product series

41

4 product series

STM32 F4 portfolio

42

STM32F4xx Block Diagram

CORTEX-M4

CPU + FPU +

MPU

168 MHz

D-bus

I-bus

S-bus

▪

▪

▪

▪

▪

▪

▪

▪

▪

▪

ARM 32-bit Cortex-M 4 CPU +FPU+MPU

up to 168 MHz

Nested Vectored Interrupt Controller (NVIC) w/ 43

maskable IT + 16 prog. priority levels

Embedded Memories :

▪

▪

FLASH: up 1Mbytes

SRAM: up 128Kbytes

CRC calculation unit

16 Channels DMA

Power Supply with internal regulator and low

power modes :

▪

▪

2V to 3V6 supply

4 Low Power Modes with Auto Wake-up

Integrated Power On Reset (POR)/Power Down

Reset (PDR) + Programmable voltage detector

(PVD)

Backup domain w/ 20B reg

JTAG/SW Debug

ETM

Nested vect IT Ctrl

1 x Systic Timer

DMA

16 Channels

Clock Control

Up to 72 MHz frequency managed & monitored by

the Clock Control

51/82/114/140 I/Os

Rich set of peripherals & IOs

▪

▪

▪

▪

▪

▪

Embedded low power RTC with VBAT capability

Dual Watchdog Architecture

17 Timers w/ advanced control features

(including Cortex SysTick)

Up to 140 I/Os (100 pin package) w/ 16

external interrupts/event

Up to 3x12-bits 2Msps ADC w/ up to 24

channels

Embedded temperature sensor w/ +/-1.5°

linearity with T°

2x6x 16-bit PWM

Synchronized AC Timer

3 x 16bit Timer

Up to 16 Ext. ITs

1 x SPI

2 x USART/LIN

AHB2 (max 168MHz)

F

/

I

h

s

a

F

l

512kB- 1MB

Flash Memory

128KB SRAM

External Memory

Interface

USB 2.0 OTG

FS/HS

Ethernet MAC

10/100, IEEE1588

x

i

r

t

a

m

s

u

b

B

H

A

-

i

t

l

u

m

t

i

b

-

2

3

®

M

R

A

)

z

H

M

0

5

1

x

a

m

(

r

e

t

i

b

r

A

AHB1

(max 168MHz)

Bridge

A

P

B

2

(

m

a

x

8

4

M

H

z

)

Bridge

APB1 (max 42MHz)

5x 16-bit Timer

2x 32-bit Timer

2x Watchdog

(independent & window)

1x SDIO

3x 12-bit ADC

24 channels / 2Msps

Temp Sensor

Encryption**

Camera Interface

USB 2.0 OTG FS

Power Supply

Reg 1.2V

POR/PDR/PVD

XTAL oscillators

32KHz + 8~25MHz

Int. RC oscillators

32KHz + 16MHz

PLL

RTC / AWU

4KB backup RAM

2x DAC + 2 Timers

2x CAN 2.0B

2 x SPI / I2S

4x USART/LIN

3x I2C

system Bus : ARM On-Chip

 AMBA: Advanced Microcontroller Bus Architecture

 AHB: Advanced High-performance Bus → AHB1 & AHB2 (168MHz)

 APB: Advanced Peripheral Bus → AP1 ( 42MHz) & AP2 (84MHz)

44

STM32F4xx Block Diagram

▪ Up to 15 communication

interfaces

– Up to 3 × I2C interfaces

– Up to 4 USARTs/2 UARTs

– Up to 3 SPIs (37.5 Mbits/s),

– 2 × CAN interfaces (2.0B Active)

– SDIO interface

■ Advanced connectivity

– USB 2.0 full-speed device

– USB 2.0 high-speed/full-speed

device

– 10/100 Ethernet MAC■ 8- to 14-

bit parallel camera interface up to

54 Mbytes/s

CORTEX-M4

CPU + FPU +

MPU

168 MHz

D-bus

I-bus

S-bus

JTAG/SW Debug

ETM

Nested vect IT Ctrl

1 x Systic Timer

DMA

16 Channels

Clock Control

51/82/114/140 I/Os

2x6x 16-bit PWM

Synchronized AC Timer

3 x 16bit Timer

Up to 16 Ext. ITs

1 x SPI

2 x USART/LIN

AHB2 (max 168MHz)

F

/

I

h

s

a

F

l

512kB- 1MB

Flash Memory

128KB SRAM

External Memory

Interface

USB 2.0 OTG

FS/HS

Ethernet MAC

10/100, IEEE1588

x

i

r

t

a

m

s

u

b

B

H

A

-

i

t

l

u

m

t

i

b

-

2

3

®

M

R

A

)

z

H

M

0

5

1

x

a

m

(

r

e

t

i

b

r

A

AHB1

(max 168MHz)

Bridge

A

P

B

2

(

m

a

x

8

4

M

H

z

)

Bridge

APB1 (max 42MHz)

5x 16-bit Timer

2x 32-bit Timer

2x Watchdog

(independent & window)

1x SDIO

3x 12-bit ADC

24 channels / 2Msps

Temp Sensor

Encryption**

Camera Interface

USB 2.0 OTG FS

Power Supply

Reg 1.2V

POR/PDR/PVD

XTAL oscillators

32KHz + 8~25MHz

Int. RC oscillators

32KHz + 16MHz

PLL

RTC / AWU

4KB backup RAM

2x DAC + 2 Timers

2x CAN 2.0B

2 x SPI / I2S

4x USART/LIN

3x I2C

Bibliography

 http://infocenter.arm.com

 Reference Manual du STM32F4 RM0090 ( 1315 pages

d’explication) disponible sur le site de ST

http://www.st.com/content/st_com/en/products/microco

ntrollers/stm32-32-bit-arm-cortex-mcus/stm32-high-

performance-mcus/stm32f4-series/stm32f407-

417/stm32f407vg.html

46